The present invention relates to a manufacturing technology of a semiconductor device, and for example, to a technology effective in applying to assembly of a semiconductor device having a semiconductor chip in which through electrodes have been formed.
For example, in Japanese Patent Laid-Open No. 2009-260373 (Patent Document 1), there is disclosed a structure in which an alignment mark is formed on a surface where a pad of a semiconductor chip has been formed, and in which the alignment mark is used as a test-dedicated pad which a probe and the like touch.
In addition, for example, in Japanese Patent Laid-Open No. 2005-175263 (Patent Document 2), there is disclosed a technology in which alignment marks that are formed in the same step as a step of forming through electrodes and that have the same structure as each other are formed on a substrate, and in which alignment of a semiconductor chip to be stacked and the substrate is performed using the alignment marks.
In addition, for example, in Japanese Patent Laid-Open No. 2011-49318 (Patent Document 3), there is disclosed a structure in which a plurality of circuit regions is formed on an upper surface of a wafer, and in which an alignment mark is provided inside the respective circuit regions, and furthermore, it is described in this Patent Document 3 that tips of through electrodes formed on the wafer can be used as the alignment marks.
In addition, for example, it is disclosed in Japanese Patent Laid-Open No. 2008-153499 (Patent Document 4) that elements, constituting a semiconductor circuit, such as a transistor and a resistor, and wirings that should be coupled to the elements are sequentially formed on a semiconductor wafer on the basis of alignment marks, and that through-holes are formed in the semiconductor wafer, and electrodes and through electrodes are formed.